The invention relates generally to pipelined computer apparatus and methods and in particular to a method and apparatus for handling data table look-aside buffer misses in a data processing equipment using virtual address data.
Substantially all multi-user computers employ virtual memory systems. These systems provide substantially unlimited memory addressing space. Typically, the processors, however, operate to the on-board high speed physical memory available to them. The on-board memory can, for example, be dedicated to a user and each time a user changes, the entire on-board memory is swapped, storing the data associated with one user in, for example, disk memory, and reading and storing data for the next user in physical memory.
In a Trace computer, such as that described hereinafter and based upon methods developed in part at Yale University, the data processor has a pipelined CPU and a pipelined memory. Further, the CPU generates virtual addresses, not physical addresses, and employs a data translation lookaside buffer (TLB) to effect a virtual address to physical address translation. It is important in such a system, which also provides for parallel processing using a very long instruction word having a length of, for example, 1,000 or more bits, to provide the address translation without a major sacrifice of either available pipeline depth or time.
A noted above, when multiple users are present, memory is typically swapped between fast physical memory and slower storage such as disk, so that for each change of user there is a change of memory. This results in an undesirable decrease of system performance. Furthermore, when a pipelined memory system is employed, a determination that the required memory data is not available in high speed physical memory can cause a yet larger degradation in system performance since the memory pipeline must be drained and the entire system reset to the instruction having a data miss.
It is therefore a primary object of the invention to provide a data processing method and apparatus for addressing a pipelined memory which provides high speed data TLB recovery when a miss occurs during a virtual address to physical address translation. Another primary object of the invention is a data TLB which minimizes user hashing. Other objects of the invention are a method and apparatus which enable reliable and efficient system recovery of a pipeline memory after a data TLB miss. Further objects of the invention are a computing method and apparatus which are reliable, fast, and capable of operating in a parallel processing environment.